Loading...
Please wait, while we are loading the content...
Similar Documents
Defect level evaluation in an ic design environment (1996).
| Content Provider | CiteSeerX |
|---|---|
| Author | Sousa, J. J. T. Gonçalves, F. M. Teixeira, J. P. Marzocca, C. Corsi, F. Williams, T. W. |
| Abstract | The purpose of this paper is to present a methodology for the evaluation of the Defect Level in an IC design environment. The methodology is based on the extension of Williams-Brown formula to non equiprobable faults, which are collected from the IC layout, using the information on a typical IC process line defect statistics. The concept of weighted fault coverage is introduced, and the Defect Level (DL) evaluated for the Poisson and the negative binomial yield models. It is shown that DL depends on the critical areas associated with undetected faults, and their correspondent defect densities. Simulation results are presented, which highlight that the classic single Line Stuck-At (LSA) fault coverage is a unreliable metric of test quality. Moreover, results show that the eciency of a given set of test patterns strongly depends on the physical design and defect statistics. 0.1 Introduction In order to achieve the high standards of electronic products quality, it is mandatory to evaluat... |
| File Format | |
| Publisher Date | 1996-01-01 |
| Access Restriction | Open |
| Subject Keyword | Ic Design Environment Defect Level Evaluation Defect Level Williams-brown Formula Ic Layout Weighted Fault Coverage Simulation Result Test Pattern Undetected Fault Test Quality High Standard Physical Design Negative Binomial Yield Model Equiprobable Fault Fault Coverage Correspondent Defect Density Critical Area Classic Single Line Stuck-at Electronic Product Quality Defect Statistic |
| Content Type | Text |
| Resource Type | Article |
