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A High-Speed MAP Architecture With Optimized Memory Size And Power Consumption (2000)
Content Provider | CiteSeerX |
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Author | Worm, Alexander Lamm, Holger Wehn, Norbert |
Description | This paper presents a novel high-speed maximum a posteriori (MAP) decoder architecture with optimized memory size and power consumption. Area and power consumption are both reduced significantly, compared to the state-of-the-art. The architecture is also capable of decoding recursive systematic convolutional codes which are the constituent codes of the revolutionary Turbo-Codes and related concatenation schemes. The architecture is highly scalable with respect to throughput, expanding its applicability over a wide range of throughput requirements (300 Mbit/s--45 Gbit/s and above). INTRODUCTION The MAP algorithm is a maximum-likelihood decoding method which minimizes the probability of symbol (or bit) error. In other words, a MAP decoder finds for each time-step the most likely information bit to have been transmitted given a received noisy or distorted sequence, thus minimizing the bit-error rate (BER). This is unlike a Viterbi decoder [1] which finds the most likely information bit ... |
File Format | |
Language | English |
Publisher Date | 2000-01-01 |
Publisher Institution | In Proc. SiPS 2000 |
Access Restriction | Open |
Subject Keyword | Decoder Architecture Bit-error Rate Constituent Code Novel High-speed Maximum Wide Range Viterbi Decoder Related Concatenation Scheme Throughput Requirement Revolutionary Turbo-codes Recursive Systematic Convolutional Code Maximum-likelihood Decoding Method Map Decoder Find Received Noisy Power Consumption Optimized Memory Size Map Algorithm Likely Information Bit High-speed Map Architecture |
Content Type | Text |
Resource Type | Article |