Loading...
Please wait, while we are loading the content...
Similar Documents
Renesting Single Appearance Schedules to Minimize Buffer Memory (1995)
| Content Provider | CiteSeerX |
|---|---|
| Author | Lee, Edward A. Bhattacharyya, Shuvra S. Murthy, Praveen K. |
| Description | Memo UCB/ERL M95/43, Electronics Research Lab |
| Abstract | Minimizing memory requirements for program and data are critical objectives when synthesizing software for embedded DSP applications. In prior work, it has been demonstrated that for graphical DSP programs based on the widely-used synchronous dataflow model, an important class of minimum code size implementations can be viewed as parenthesizations of lexical orderings of the computational blocks. Such a parenthesization corresponds to the hierarchy of loops in the software implementation. In this paper, we present a dynamic programming technique for constructing a parenthesization that minimizes data memory cost from a given lexical ordering of a synchronous dataflow graph. For graphs that do not contain delays on the edges, this technique always constructs a parenthesization that has minimum data memory cost from among all parenthesizations for the given lexical ordering. When delays are present, the technique may make refinements to the lexical ordering while it is computing the pare... |
| File Format | |
| Publisher Date | 1995-01-01 |
| Access Restriction | Open |
| Subject Keyword | Critical Objective Important Class Embedded Dsp Application Software Implementation Computational Block Single Appearance Schedule Lexical Ordering Minimize Buffer Memory Prior Work Graphical Dsp Program Memory Requirement Synchronous Dataflow Graph Dynamic Programming Technique Minimum Code Size Implementation Widely-used Synchronous Dataflow Model Data Memory Cost |
| Content Type | Text |
