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Fast Evaluation Method for Transient Hot Spots (2008)
| Content Provider | CiteSeerX |
|---|---|
| Author | Park, Je-Hyoung Shakouri, Ali Kang, Sung-Mo |
| Description | Recently VLSI IC design is concerned with the large temperature non-uniformity in high power chips. Thus far, thermal simulations have been limited to steady-state worst case conditions, which have caused the use of conservative margins in thermal designs. Transient temperature characteristics were not simulated in prior art chip-level simulations due to the high computational expense. To drastically reduce the time for the chip-level thermal simulations, we have developed a matrix convolution technique, called the Power Blurring (PB) method. Our method renders the temperature profile of a packaged IC with maximum error less than 3 % for several case studies done and reduces the computation time by a factor of 100, compared to the simulations done by the industry standard finite element tools. 1. |
| File Format | |
| Language | English |
| Publisher Date | 2008-01-01 |
| Publisher Institution | in VLSI ICs in Packages” 9th International Symposium on Quality Electronic Design (ISQED 08 |
| Access Restriction | Open |
| Subject Keyword | Conservative Margin High Computational Expense Transient Temperature Characteristic Thermal Simulation Industry Standard Finite Element Tool Temperature Profile Several Case Study Steady-state Worst Case Condition Chip-level Thermal Simulation Computation Time Transient Hot Spot Vlsi Ic Design Thermal Design Power Blurring Maximum Error Fast Evaluation Method High Power Chip Matrix Convolution Technique Prior Art Chip-level Simulation Large Temperature Non-uniformity |
| Content Type | Text |
| Resource Type | Article |
