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Fast scalable fpga-based network-on-chip simulation models.
| Content Provider | CiteSeerX |
|---|---|
| Author | Papamichael, Michael K. |
| Abstract | Abstract—This paper presents a set of two FPGA-based Network-on-Chip (NoC) simulation engines that composed the winning design of the 2011 MEMOCODE Design Contest in the absolute performance class. Both simulation engines were developed in Bluespec System Verilog (BSV) and were implemented on a Xilinx ML605 FPGA development board. For smaller networks and simpler router configurations a directmapped approach was employed, where the network to be simulated was directly implemented on the FPGA. For larger networks, where a direct-mapped approach is not feasible due to FPGA resource limitations, a virtualized time-multiplexed approach was used. Compared to the provided software reference implementation, our direct-mapped approach achieves three orders of magnitude speedup, while our virtualized timemultiplexed approach achieves one to two orders of magnitude speedup, depending on the network and router configuration. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Simulation Engine Magnitude Speedup Fpga-based Network-on-chip Software Reference Implementation Virtualized Timemultiplexed Approach Xilinx Ml605 Fpga Development Board Absolute Performance Class Fpga Resource Limitation Direct-mapped Approach Achieves Virtualized Time-multiplexed Approach Simpler Router Configuration Router Configuration Memocode Design Contest Bluespec System Verilog Direct-mapped Approach Directmapped Approach |
| Content Type | Text |
