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A Scalable Approach to Thread-Level Speculation (2000)
| Content Provider | CiteSeerX |
|---|---|
| Author | Steffan, J. Gregory Colohan, Christopher B. Zhai, Antonia Mowry, Todd C. |
| Description | In Proceedings of the 27th Annual International Symposium on Computer Architecture While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the real challenge is how to easily create parallel software to effectively exploit all of this raw performancepotential. One promising technique for overcoming this problem is Thread-Level Speculation (TLS), which enables the compiler to optimistically create parallel threads despite uncertainty as to whether those threads are actually independent. In this paper, we propose and evaluate a design for supporting TLS that seamlessly scales to any machine size because it is a straightforward extension of writeback invalidation-based cache coherence (which itself scales both up and down). Our experimental results demonstrate that our scheme performs well on both single-chip multiprocessors and on larger-scale machines where communication latencies are twenty times larger. 1. Introduction Machines which can simultaneou... |
| File Format | |
| Language | English |
| Publisher Date | 2000-01-01 |
| Access Restriction | Open |
| Subject Keyword | Real Challenge Promising Technique Wide Spectrum Writeback Invalidation-based Cache Coherence Scheme Performs Cost-effective Parallel Machine Parallel Thread Single Chip Scalable Approach Machine Size Large-scale Server Communication Latency Straightforward Extension Thread-level Speculation Larger-scale Machine Parallel Software Introduction Machine Raw Performancepotential Experimental Result Twenty Time Single-chip Multiprocessor |
| Content Type | Text |
| Resource Type | Article |
