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Practical considerations for the design of cascade multi-bit high-frequency (1998).
| Content Provider | CiteSeerX |
|---|---|
| Author | Del, Modulators Medeiro Medeiro, F. Ro, R. Del Prez-Verd, B. Rodrguez-Vzquez, A. Microelectrnica, Nacional |
| Abstract | Recommendations are given for efficient design of highfrequency SD modulators using multi-stage (cascade) multi-bit quantization architectures. These cover from pure architectural aspects to cell design with special emphasis on the impact of circuit imperfections. Conclusions are validated by measurements on a 13-bit 2.2MS/s prototype fabricated in a 0.7m CMOS technology. 1. Introduction Nowadays, several industrial applications have renewed the interest on extending the use of SD modulators (SDM's) up to the communication range and above [1]. In fact, using oversampling and noise-shaping techniques for high-performance A/D conversion is becoming more and more attractive as poor-analog-performance technologies are imposed. However, because the signal bandwidth and the sampling frequency of a SD converter are related through the oversampling ratio , increasing the signal frequency while keeping achievable sampling frequency and low-power consumption implies a reduction of M required... |
| File Format | |
| Publisher Date | 1998-01-01 |
| Access Restriction | Open |
| Subject Keyword | Practical Consideration Cascade Multi-bit High-frequency Communication Range Circuit Imperfection Several Industrial Application Cmos Technology Pure Architectural Aspect Sd Converter Poor-analog-performance Technology Efficient Design Noise-shaping Technique Sd Modulators Highfrequency Sd Modulators Multi-bit Quantization Architecture Achievable Sampling Frequency Introduction Nowadays Oversampling Ratio Signal Bandwidth Special Emphasis High-performance Conversion Signal Frequency Sampling Frequency |
| Content Type | Text |
