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OWL: Cooperative Thread Array Aware Scheduling Techniques for Improving GPGPU Performance (2013)
| Content Provider | CiteSeerX |
|---|---|
| Author | Jog, Adwait Kayiran, Onur Mishra, Aneil K. Mahmut T., K. |
| Description | Emerging GPGPU architectures, along with programming models like CUDA and OpenCL, offer a cost-effective platform for many applications by providing high thread level parallelism at lower energy budgets. Unfortunately, for many general-purpose applications, available hardware resources of a GPGPU are not efficiently utilized, leading to lost opportunity in improving performance. A major cause of this is the inefficiency of current warp scheduling policies in tolerating long memory latencies. In this paper, we identify that the scheduling decisions made by such policies are agnostic to thread-block, or cooperative thread array (CTA), behavior, and as a result inefficient. We present a coordinated CTA-aware scheduling policy that utilizes four schemes to minimize the impact of long memory latencies. The first two schemes, CTA-aware two-level warp scheduling and locality aware warp scheduling, enhance per-core performance by effectively reducing cache contention and improving latency hiding capability. The third scheme, bank-level parallelism aware warp scheduling, improves overall GPGPU performance by enhancing DRAM bank-level parallelism. The fourth scheme employs opportunistic memory-side prefetching to further enhance performance by taking advantage of open DRAM rows. Evaluations on a 28-core GPGPU platform with highly memory-intensive applications indicate that our proposed mechanism can provide 33 % average performance improvement compared to the commonly-employed round-robin warp scheduling policy. In ASPLOS |
| File Format | |
| Language | English |
| Publisher Date | 2013-01-01 |
| Access Restriction | Open |
| Subject Keyword | Open Dram Row Commonly-employed Round-robin Warp Scheduling Policy Many General-purpose Application Coordinated Cta-aware Scheduling Policy Many Application Energy Budget Bank-level Parallelism Aware Warp Scheduling Average Performance Improvement Opportunistic Memory-side Prefetching Major Cause Improving Gpgpu Performance Overall Gpgpu Performance High Thread Level Parallelism Current Warp Available Hardware Resource Dram Bank-level Parallelism Cache Contention Per-core Performance Cost-effective Platform Result Inefficient Long Memory Latency Locality Aware Warp Scheduling Third Scheme 28-core Gpgpu Platform Cta-aware Two-level Warp Scheduling Fourth Scheme Memory-intensive Application Cooperative Thread Array Scheduling Decision Gpgpu Architecture Enhance Performance |
| Content Type | Text |
| Resource Type | Article |
