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The Effect of Wire Length Minimization on Yield (1994)
| Content Provider | CiteSeerX |
|---|---|
| Author | Chiluvuri, Venkat K. R. Koren, Israel Burns, Jeffrey L. |
| Description | Wire length minimization ( WLM) has received szgnificant attention in the compaction stage of VLSI layout synthesis. In most cases, reduction in wire length also results in better circuit yield. However, a trade-off may stall exist between total wire length and yield. In WLM only the area/length of the layout patterns is considered whereas for yield enhancement both the area of the layout patterns and the spacing among them must be considered. The trade-off between these two features is analyzed on a set of benchmark layouts in this paper. 1 IEEE mi. Workshop on Defeci and Fault Tolerance in VLSI Systems |
| File Format | |
| Language | English |
| Publisher Date | 1994-01-01 |
| Access Restriction | Open |
| Subject Keyword | Yield Enhancement Wire Length Szgnificant Attention Total Wire Length Area Length Benchmark Layout Layout Pattern Wire Length Minimization Circuit Yield Compaction Stage |
| Content Type | Text |
| Resource Type | Article |
