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Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability (1996)
| Content Provider | CiteSeerX |
|---|---|
| Author | Cheng, Kwang-Ting Krstic, Angela |
| Abstract | Path delay fault model is the most suitable model for detecting distributed manufacturing defects that can cause delay faults. However, the number of paths in a modern design can be extremely large and the path delay testability of many practical designs could be very low. In this paper we show how to resynthesize a combinational circuit in order to reduce the total number of paths. Our results show that it is possible to obtain circuits with a signi#cant reduction in the number of paths while not increasing area and#or delay of the longest sensitizable path in the circuit. Research on path delay testing shows that in many circuits a large portion of paths does not have a test that can guarantee detection of a delay fault. The path delay testability of a circuit would increase if the number of such paths is reduced. We show that addition of a small number of test points can help reducing the number of such paths in the given design. 1 Introduction The goal of delay testing is to det... |
| File Format | |
| Publisher Date | 1996-01-01 |
| Publisher Institution | Jour. of Electronic Testing: Theory and Applications |
| Access Restriction | Open |
| Subject Keyword | Path Delay Fault Testability Path Delay Fault Model Many Practical Design Distributed Manufacturing Defect Total Number Signi Cant Reduction Test Point Path Delay Testability Small Number Many Circuit Sensitizable Path Modern Design Path Delay Delay Testing Combinational Circuit Delay Fault Large Portion Path Count Reduction Suitable Model |
| Content Type | Text |
| Resource Type | Article |
