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A Low Latency Router Supporting Adaptivity for On-Chip (2005)
| Content Provider | CiteSeerX |
|---|---|
| Author | Kim, Jongman Park, Dongkook Theocharides, T. Vijaykrishnan, N. Das, Chita R. |
| Description | The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on-Chip (NoC) have been proposed. The NoC routing algorithm significantly influences the performance and energy consumption of the chip. We propose a router architecture which utilizes adaptive routing while maintaining low latency. The two-stage pipelined architecture uses look ahead routing, speculative allocation, and optimal output path selection concurrently. The routing algorithm benefits from congestionaware flow control, making better routing decisions. We simulate and evaluate the proposed architecture in terms of network latency and energy consumption. Our results indicate that the architecture is effective in balancing the performance and energy of NoC designs. |
| File Format | |
| Language | English |
| Publisher Date | 2005-01-01 |
| Publisher Institution | Interconnects, ” ACM Design Automation Conf. (DAC’05 |
| Access Restriction | Open |
| Subject Keyword | Algorithm Benefit Speculative Allocation Optimal Output Path Selection Proposed Architecture Energy Consumption Noc Design System-on-chip Design Network Latency Potential Solution Increased Deployment Router Architecture On-chip Interconnects Low Latency Low Latency Router Supporting Adaptivity Congestionaware Flow Control Two-stage Pipelined Architecture |
| Content Type | Text |
| Resource Type | Article |
