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Study of a multilevel approach to partitioning for parallel logic simulation (2000)
| Content Provider | CiteSeerX |
|---|---|
| Author | Subramanian, Swaminathan Rao, Dhananjai M. Wilsey, Philip A. |
| Description | Parallel simulation techniques are often employed to meet the computational requirements of large hardware simulations in order to reduce simulation time. In addition, partitioning for parallel simulations has been shown to be vital for achieving higher simulation throughput. This paper presents the results of our partitioning studies conducted on an optimistic parallel logic simulation framework based on the Time Warp synchronization protocol. The paper also presents the design and implementation of a new partitioning algorithm based on a multilevel heuristic, developed as a part of this study. The multilevel algorithm attempts to balance load, maximize concurrency, and reduce inter-processor communication in three phases to improve performance. The experimental results obtained from our benchmarks indicate that the multilevel algorithm yields better partitions than other partitioning algorithms included in the study. 1 |
| File Format | |
| Language | English |
| Publisher | Society Press |
| Publisher Date | 2000-01-01 |
| Publisher Institution | In International Parallel and Distributed Processing Symposium, (IPDPS'00). IEEE Computer |
| Access Restriction | Open |
| Subject Keyword | Simulation Throughput Parallel Logic Simulation Multilevel Approach Large Hardware Simulation Time Warp Synchronization Protocol Multilevel Algorithm Attempt Simulation Time Computational Requirement Experimental Result Parallel Simulation Technique Multilevel Heuristic Multilevel Algorithm Yield Optimistic Parallel Logic Simulation Framework Inter-processor Communication Parallel Simulation |
| Content Type | Text |
| Resource Type | Article |
