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Synthesis under Local Timing Constraints in the CAMAD High-Level Synthesis System (1995)
| Content Provider | CiteSeerX |
|---|---|
| Author | Hallberg, Jonas Peng, Zebo |
| Description | This paper describes a technique to use local timing constraints to drive the high-level synthesis process, which has been implemented in the CAMAD system. A design is represented with an Extended Timed Petri Net (ETPN) and local timing constraints are introduced as special arcs, in the control part of the ETPN. A method for checking the consistency of a given set of local timing constraints is described as well as an algorithm that schedules the operations in such a way that the timing constraints are fulfilled. Together with the possibility to compile behavioral VHDL to ETPN this work is a step towards a system that allows high-level behavioral specifications including timing constraints to be efficiently compiled into silicon. This work has been supported by the Swedish National Board for Industrial and Technical Development (NUTEK). Accepted to the 21st EUROMICRO conference Como, Italy, September 4-7, 1995 1995 95-34 1. Introduction In this paper, the concept of lo... In the CAMAD High-Level Synthesis System, Proc. of IEEE EUROMICRO 95 |
| File Format | |
| Language | English |
| Publisher Date | 1995-01-01 |
| Access Restriction | Open |
| Subject Keyword | Extended Timed Petri Net Euromicro Conference Como Swedish National Board Local Timing Constraint Camad System Camad High-level Synthesis System Control Part High-level Behavioral Specification High-level Synthesis Process Behavioral Vhdl Timing Constraint Special Arc Technical Development |
| Content Type | Text |
| Resource Type | Article |
