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Modeling communication in cache-coherent smp systems- a case-study with xeon phi ∗ abstract.
| Content Provider | CiteSeerX |
|---|---|
| Author | Ramos, Sabela |
| Abstract | Most multi-core and some many-core processors implement cachecoherencyprotocolsthatheavilycomplicatethedesign of optimal parallel algorithms. Communication is performed implicitly by cache line transfers between cores, complicating the understanding of performance properties. We developed an intuitive performance model for cache-coherent architectures and demonstrate its use with the currently most scalable cache-coherent many-core architecture, Intel Xeon Phi. Using our model, we develop several optimal and optimized algorithms for complex parallel data exchanges. All algorithmsthat were developed with the modelbeat the performance of the highly-tuned vendor-specific Intel OpenMP and MPI libraries by up to a factor of 4.3. The model can be simplified to satisfy the tradeoff between complexity of algorithm design and accuracy. We expect that our model can serve as a vehicle for advanced algorithm design. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Cache-coherent Smp Xeon Phi Abstract Optimal Parallel Algorithm Intuitive Performance Model Cache Line Transfer Cache-coherent Architecture Performance Property Highly-tuned Vendor-specific Intel Openmp Scalable Cache-coherent Many-core Architecture Advanced Algorithm Design Optimized Algorithm Mpi Library Algorithm Design Complex Parallel Data Exchange Intel Xeon Phi Many-core Processor Implement |
| Content Type | Text |
