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Teaching basics of instruction pipelining with hdldlx.
| Content Provider | CiteSeerX |
|---|---|
| Author | Bečvář, Miloš |
| Abstract | Abstract: HDLDLX is a graphically described VHDL model of 5-stage integer pipeline of well known DLX processor. It can be used as a platform explaining logic-level implementation of pipelined processor as a complement to SW functional simulators. Students can interact with model by implementing hazard resolution logic or modifying the pipeline structure. Even though that the model is internally represented in VHDL, the previous knowledge of this language is not required. HDLDLX can be used in conjunction with HDL Designer and Modelsim tools from Mentor Graphics corporation. Article also discusses pros and cons of using commercial EDA tools in undergraduate computer architecture course. 1. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Dlx Processor Pipeline Structure Undergraduate Computer Architecture Course Mentor Graphic Corporation Previous Knowledge 5-stage Integer Pipeline Commercial Eda Tool Modelsim Tool Pipelined Processor Vhdl Model Sw Functional Simulator Logic-level Implementation Hazard Resolution Logic Hdl Designer |
| Content Type | Text |
| Resource Type | Article |
