Loading...
Please wait, while we are loading the content...
Similar Documents
Capacity (gb) latency (ns) tiered-latency dram: a low latency and low cost dram architecture.
| Content Provider | CiteSeerX |
|---|---|
| Author | Lee, Donghyuk Kim, Yoongu Seshadri, Vivek Liu, Jamie Subramanian, Lavanya Mutlu, Onur |
| Abstract | The capacity and cost-per-bit of DRAM have historically scaled to satisfy the needs of increasingly large and complex computer systems. However, DRAM latency has remained almost constant, making memory latency the performance bottleneck in today’s systems. We observe that the high access latency is not intrinsic to DRAM, but a trade-off made to decrease cost-per-bit. To mitigate the high area overhead of DRAM sensing structures, commodity DRAMs connect many DRAM cells to each sense-amplifier through a wire called a bitline. These bitlines have a high parasitic capacitance due to their long length, and this bitline capacitance is the dominant source of DRAM latency. Specialized low-latency DRAMs use shorter bitlines with fewer cells, but have a higher cost-per-bit due to greater senseamplifier area overhead. In this work, we introduce Tiered-Latency DRAM (TL-DRAM), which achieves both low latency and low cost-per-bit. In TL-DRAM, each long bitline is split into two shorter segments by an isolation transistor, allowing one segment to be accessed with the latency of a short-bitline DRAM without incurring high cost-per-bit. We propose mechanisms that use the low-latency segment as a hardware-managed or software-managed cache. Evaluations show that our proposed mechanisms improve both performance and energy-efficiency for both single-core and multi-programmed workloads. 1 |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Low Latency Tiered-latency Dram Low Cost Dram Architecture Dram Latency Long Bitline Long Length Multi-programmed Workload Low-latency Segment Dominant Source Complex Computer System Software-managed Cache High Area Overhead Memory Latency High Access Latency Area Overhead Today System Isolation Transistor Bitline Capacitance Low Cost-per-bit Performance Bottleneck High Cost-per-bit Short-bitline Dram High Parasitic Capacitance Commodity Dram Many Dram Cell |
| Content Type | Text |
