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Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates (1999)
| Content Provider | CiteSeerX |
|---|---|
| Author | Sasao, Tsutomu Debnath, Debatosh |
| Abstract | This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP) for multiple-valued input two-valued output functions. We present techniques to minimize EX-SOPs, which is an extension of Dubrova-Miller-Muzio's AOXMIN algorithm. We conjecture that, when n is sufficiently large, an EX-SOP for n-bit adder requires at most 2 n products while an ordinary sumof -products expression (SOP) requires 6 \Delta 2 n ; 4n ; 5 products. Experimental results for two- and four-valued benchmark functions show that the proposed method produces better EX-SOPs than existing methods. |
| File Format | |
| Publisher Date | 1999-01-01 |
| Access Restriction | Open |
| Subject Keyword | Ordinary Sumof Product Expression Aoxmin Algorithm Output Exor Gate N-bit Adder Sum-of-products Expression Optimization Method Programmable Logic Array Four-valued Benchmark Function Multiple-valued Minimization Present Technique Experimental Result Multiple-valued Input Two-valued Output Function Two-input Exor Gate |
| Content Type | Text |
| Resource Type | Article |
