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Cheri: a research platform deconflating hardware virtualization and protection.
| Content Provider | CiteSeerX |
|---|---|
| Author | Watson, Robert N. M. Neumann, Peter G. Woodruff, Jonathan Anderson, Jonathan Anderson, Ross Dave, Nirav Laurie, Ben Moore, Simon W. Murdoch, Steven J. Paeps, Philip Roe, Michael Saidi, Hassen |
| Abstract | Contemporary CPU architectures conflate virtualization and protection, imposing virtualization-related performance, programmability, and debuggability penalties on software requiring finegrained protection. First observed in micro-kernel research, these problems are increasingly apparent in recent attempts to mitigate software vulnerabilities through application compartmentalisation. Capability Hardware Enhanced RISC Instructions (CHERI) extend RISC ISAs to support greater software compartmentalisation. CHERI’s hybrid capability model provides fine-grained compartmentalisation within address spaces while maintaining software backward compatibility, which will allow the incremental deployment of fine-grained compartmentalisation in both our most trusted and least trustworthy C-language software stacks. We have implemented a 64-bit MIPS research soft core, BERI, as well as a capability coprocessor, and begun adapting commodity software packages (FreeBSD and Chromium) to execute on the platform. 1. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Hardware Virtualization Research Platform Fine-grained Compartmentalisation Recent Attempt Software Vulnerability Commodity Software Package Software Compartmentalisation Cheri Hybrid Capability Model Contemporary Cpu Architecture Risc Isas Micro-kernel Research Virtualization-related Performance Capability Coprocessor 64-bit Mips Research Soft Core Debuggability Penalty Incremental Deployment Application Compartmentalisation Trustworthy C-language Software Stack Capability Hardware Enhanced Risc Instruction Software Backward Compatibility Address Space |
| Content Type | Text |