NDLI: Architectural power management for battery lifetime optimization in portable systems.

Please wait, while we are loading the content...

Architectural power management for battery lifetime optimization in portable systems.

Content Provider	CiteSeerX
Author	Kulkarni, Manish Agrawal, Vishwani D.
Abstract	For portable computing devices, maximizing battery lifetime or performing maximum possible operations per recharge is a primary objective. Various voltage and frequency scaling techniques are being used in commercial devices. This work considers the role of energy source, i.e., battery, in the optimization of a portable system. We introduce battery lifetime in number of clock cycles as an optimization metric. In addition the energy consumed by the system, battery lifetime also depends upon the battery efficiency, which may degrade as the power consumption increases. We examine power reduction techniques for a processor such as frequency scaling, i.e., clock slowdown (CSD) and instruction slowdown (ISD) from a battery efficiency viewpoint and estimate battery lifetime expressed in number of operational cycles. In case of ISD, implemented with the help of NOPs, we demonstrate that the lifetime for a given size of battery might be optimum at a slowdown factor around 2 to 3. The battery lifetime improvement requires reduced power dissipation coupled with prolonged execution time and, surprisingly, sometimes even increased energy consumption. With architecture level modifications, such as instruction slowdown, battery lifetime increase of 20 % is realized.
File Format	PDF
Access Restriction	Open
Subject Keyword	Portable System Battery Lifetime Optimization Architectural Power Management Instruction Slowdown Battery Lifetime Energy Consumption Battery Lifetime Improvement Power Consumption Increase Prolonged Execution Time Slowdown Factor Battery Efficiency Viewpoint Clock Slowdown Various Voltage Power Reduction Technique Maximum Possible Operation Estimate Battery Lifetime Frequency Scaling Frequency Scaling Technique Battery Lifetime Increase Reduced Power Dissipation Commercial Device Energy Source Clock Cycle Architecture Level Modification Battery Efficiency Primary Objective Operational Cycle
Content Type	Text

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in