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Hierarchical Overlapped Tiling
| Content Provider | CiteSeerX |
|---|---|
| Author | Giacalone, Jean-Pierre Garzarán, María Jesús Kuhn, Robert H. Ni, Yang Padua, David Zhou, Xing |
| Abstract | This paper introduces hierarchical overlapped tiling, a transformation that applies loop tiling and fusion to conventional loops. Overlapped tiling is a useful transformation to reduce communication overhead, but it may also generate a significant amount of redundant computation. Hierarchical overlapped tiling performs overlapped tiling hierarchically to balance communication overhead and redundant computation, and thus has the potential to provide better performance. In this paper, we describe the hierarchical overlapped tiling optimization and its implementation in an OpenCL compiler. We also evaluate the effectiveness of this optimization using 8 programs that implement different forms of stencil computation. Our results show that hierarchical overlapped tiling achieves an average 37 % speedup over traditional tiling on a 32-core workstation. Categories and Subject Descriptors |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Significant Amount Opencl Compiler Loop Tiling Conventional Loop Overlapped Tiling Redundant Computation 32-core Workstation Different Form Communication Overhead Useful Transformation Stencil Computation Traditional Tiling |
| Content Type | Text |
| Resource Type | Article |
