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Full Chip Characterization of Compression Algorithms for Direct Write Maskless Lithography Systems
| Content Provider | CiteSeerX |
|---|---|
| Author | Zakhor, Avideh Dai, Vito Cramer, George |
| Abstract | Future lithography systems must produce more dense microchips with smaller feature sizes, while maintaining throughput comparable to today’s optical lithography systems. This places stringent data-handling requirements on the design of any maskless lithography system. Today’s optical lithography systems transfer one layer of data from the mask to the entire wafer in about sixty seconds. To achieve a similar throughput for a direct-write maskless lithography system with a pixel size of 22 nm, data rates of about 12 Tb/s are required. Over the past 8 years, we have proposed a datapath architecture for delivering such a data rate to a parallel array of writers. Our proposed system achieves this data rate contingent on two assumptions: consistent 10 to 1 compression of lithography data, and implementation of real-time hardware decoder, fabricated on a microchip together with a massively parallel array of lithography writers, capable of decoding 12 Tb/s of data. To address the compression efficiency problem, in the past few years, we have developed a new technique, Context Copy Combinatorial Coding (C4), designed specifically for microchip layer images, with a low-complexity decoder for application to the datapath architecture. C4 combines the advantages of JBIG and ZIP, to achieve compression ratios higher than existing techniques. We have also devised Block C4, a variation of C4 with up to hundred times faster encoding times, with little or no loss in compression efficiency. While our past work has focused on characterizing the compression |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Similar Throughput Lithography Writer Compression Efficiency Compression Efficiency Problem Datapath Architecture Pixel Size Direct-write Maskless Lithography System Past Year Future Lithography System Full Chip Characterization Optical Lithography System Data Rate Context Copy Combinatorial Coding Dense Microchip Entire Wafer Block C4 Low-complexity Decoder New Technique Past Work Stringent Data-handling Requirement Compression Algorithm Data Rate Contingent Sixty Second Direct Write Maskless Lithography System Proposed System Microchip Layer Image Parallel Array Compression Ratio Maskless Lithography System Feature Size Lithography Data Real-time Hardware Decoder |
| Content Type | Text |
