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A bist architecture for at-speed dram testing.
| Content Provider | CiteSeerX |
|---|---|
| Author | Huang, Shi-Yu Kwai, Ding-Ming Huang, Chris |
| Abstract | Abstract 1 A high-speed Built-In Self-Test (BIST) architecture for Dynamic Random Access Memories (DRAMs) is proposed. The circuit automatically generates a sequence of pre-defined test patterns for on-chip DRAM testing. The innovation herein is mainly an architecture consisting of two finite state machines, instead of the conventional single finite state machine. Based upon this architecture, the pipeline technique can then be applied to divide the pattern generation process into stages, leading to a higher-speed design which is capable of testing DRAM at speed for catching delay faults. In addition to pipelining, a technique referred to as protocolbased relaxation is also incorporated. This technique, imposing a certain protocol on the two communicating finite state machines, further relaxes the timing criticality of the design. Synthesis results show that the proposed BIST circuit can operate at the speed of as high as 400MHz using 0.35um CMOS technology. 1. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | At-speed Dram Testing Bist Architecture Finite State Machine Dynamic Random Access Memory Protocolbased Relaxation Pre-defined Test Pattern Higher-speed Design Pipeline Technique Timing Criticality Certain Protocol Conventional Single Finite State Machine Cmos Technology Pattern Generation Process Delay Fault Bist Circuit High-speed Built-in Self-test Innovation Herein On-chip Dram Testing Synthesis Result |
| Content Type | Text |
