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Digital Background Correction of Harmonic Distortion in Pipelined ADCs (2006)
| Content Provider | CiteSeerX |
|---|---|
| Author | Panigada, Rea Galton, Ian |
| Abstract | Abstract—Pipelined analog-to-digital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dominant consumers of power in high-resolution pipelined ADCs. This paper presents a background calibration technique that digitally measures and cancels ADC error arising from distortion introduced by the residue amplifiers. It allows the use of higher distortion and, therefore, lower power residue amplifiers in high-accuracy pipelined ADCs, thereby significantly reducing overall power consumption relative to conventional pipelined ADCs. Index Terms—Analog-to-digital conversion, calibration, harmonic distortion, mixed analog–digital integrated circuits (ICs). |
| File Format | |
| Journal | Circuits and System I: Regular Papers, IEEE Transactions on |
| Language | English |
| Publisher Date | 2006-01-01 |
| Access Restriction | Open |
| Subject Keyword | Harmonic Distortion Residue Amplifier Digital Background Correction Pipelined Adcs Dominant Consumer Overall Power Consumption Relative Power Residue Amplifier Mixed Analog High-accuracy Pipelined Adcs Index Term Analog-to-digital Conversion Power Consumption Conventional Pipelined Adcs First Stage Background Calibration Technique Analog-to-digital Converter Cancel Adc Error |
| Content Type | Text |
| Resource Type | Article |
