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Bus-invert coding for low-power i/o (1995)
| Content Provider | CiteSeerX |
|---|---|
| Author | Stan, Mircea R. Burleson, Wayne P. |
| Abstract | Abstruct- Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit. While it is generally accepted that because of the large capacitances involved much of the power dissipated by an IC is at the U0 little has been specifically done for decreasing the U0 power dissipation. We propose the Bus-Znvert method of coding the U0 which lowers the bus activity and thus decreases the U0 peak power dissipation by 50 % and the U0 average power dissipation by up to 25%. The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power. |
| File Format | |
| Journal | IEEE Trans. VLSI Syst |
| Language | English |
| Publisher Date | 1995-01-01 |
| Access Restriction | Open |
| Subject Keyword | Bus-invert Coding Large Capacitance Bus Activity Portable Application Low-power Design Low-power Circuit U0 Average Power Dissipation Vlsi Design Physical Transformation Many Promising Result Abstruct Technology Trend U0 Peak Power Dissipation Bus-znvert Method Dynamic Power Node Capacitance Cmos Circuit U0 Power Dissipation |
| Content Type | Text |
| Resource Type | Article |
