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Maximizing TLP with loop-parallelization on SMT (2001)
| Content Provider | CiteSeerX |
|---|---|
| Author | Puppin, Diego Tullsen, Dean |
| Description | This paper describes research in exploiting loop-level parallelism on a simultaneous multithreading processor. We discuss some general and ad-hoc techniques for loop parallelization that proved to be effective with SMT, and how they were tuned for it. These techniques have been tested on the well-known Livermore loops, chosen for their variety of behaviors. The set of optimizations used produced significant improvement overall: we were able to improve average IPC from 2.72 to 3.97, and to gain an average speedup of 1.39 over optimized single-thread code, using up to eight threads. |
| File Format | |
| Language | English |
| Publisher Date | 2001-01-01 |
| Publisher Institution | In Workshop on Multi-Threaded Execution, Architectures and Compilers (MTEAC-5 |
| Access Restriction | Open |
| Subject Keyword | Well-known Livermore Loop Average Speedup Ad-hoc Technique Average Ipc Significant Improvement Simultaneous Multithreading Processor Single-thread Code Loop Parallelization Loop-level Parallelism |
| Content Type | Text |
| Resource Type | Article |
