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Tcp: tag correlating prefetchers (2003).
| Content Provider | CiteSeerX |
|---|---|
| Author | Hu, Zhigang Kaxiras, Stefanos Martonosi, Margaret |
| Abstract | Although caches for decades have been the backbone of the memory system, the speed gap between CPU and main memory suggests their augmentation with prefetching mechanisms. Recently, sophisticated hardware correlating prefetching mechanisms have been proposed, in some cases coupled with some form of dead-block prediction. In many proposals, however, correlating prefetchers demand a significant investment in hardware. In this paper we show that correlating prefetchers that work with tags instead of cache-line addresses are significantly more resource-efficient, providing equal or better performance than previous proposals. We support this claim by showing that per-set tag sequences exhibit highly repetitive patterns both within a set and across different sets. Because a single tag sequence can capture multiple address sequences spread over different cache sets, significant space savings can be achieved. We propose a tag-based prefetcher called a Tag Correlating Prefetcher (TCP). Even with very small history tables, TCP outperforms address-based correlating prefetchers many times larger. In addition, we show that such a prefetcher can yield most of its performance benefits if placed at the L2 level of an aggressive out-of-order processor. Only if one wants prefetching all the way up to L1, is dead-block prediction required. Finally, we draw parallels between the twolevel structure of TCP and similar structures for branch prediction mechanisms; these parallels raise interesting opportunities for improving correlating memory prefetchers by harnessing lessons already learned for correlating branch predictors. |
| File Format | |
| Publisher Date | 2003-01-01 |
| Access Restriction | Open |
| Subject Keyword | Prefetchers Many Time Sophisticated Hardware Multiple Address Sequence Similar Structure Memory System Repetitive Pattern Speed Gap Cache-line Address Aggressive Out-of-order Processor Twolevel Structure Tag Correlating Prefetcher Main Memory Different Cache Set Branch Prediction Mechanism Significant Space Saving Tag Correlating Prefetchers Interesting Opportunity L2 Level Previous Proposal Memory Prefetchers Tag-based Prefetcher Dead-block Prediction Performance Benefit Different Set Single Tag Sequence Significant Investment Branch Predictor Per-set Tag Sequence Small History Table Many Proposal |
| Content Type | Text |
| Resource Type | Article |
