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Simultaneous multithreading (smt) processors.
| Content Provider | CiteSeerX |
|---|---|
| Author | Jayme, Jennifer M. |
| Abstract | Different Simultaneous Multithreading (SMT) architectures have been proposed and implemented in the industry. Though, as powerful as it sounds over a superscalar processor, design issues are not rare. Addressing a certain problem can be done in hardware or in software; depending on what SMT architecture will you apply it to. Two papers are presented here. The first one, implemented in hardware a solution for wasted resources, heterogeneously clustered SMT architecture. The Heterogeneously Distributed SMT (hdSMT) architecture maximizes the hardware budget by taking into account the heterogeneity of applications. The second paper proposed an Implicitly-Multithreaded (IMT) processor utilizing SMT’s support for multithreading by executing speculative threads. It relied mostly on the compiler to select suitable thread spawning points and orchestrate interthread register communication. I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Design Issue Second Paper Suitable Thread Hardware Budget Different Simultaneous Multithreading Wasted Resource Speculative Thread Heterogeneously Distributed Smt Orchestrate Interthread Register Communication Smt Architecture Simultaneous Multithreading Smt Support Superscalar Processor Certain Problem |
| Content Type | Text |
