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Formalizing and improving dpa resistance of quasi delay insensitive asynchronous circuits.
| Content Provider | CiteSeerX |
|---|---|
| Abstract | The purpose of this paper is to formally specify a flow devoted to the design of Differential Power Analysis (DPA) resistant QDI asynchronous circuits. The paper first proposes a formal modeling of the electrical signature of QDI asynchronous circuits. The DPA is then applied to the formal model in order to identify the source of leakage of this type of circuits. Finally, a complete design flow is specified to minimize the information leakage. The relevancy and efficiency of the approach is demonstrated using the design of an AES crypto-processor. I. Introduction and motivations Since the discovery of the Power Analysis attacks such |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Formal Modeling Information Leakage Qdi Asynchronous Circuit Quasi Delay Insensitive Asynchronous Circuit Formal Model Improving Dpa Resistance Electrical Signature Aes Crypto-processor Power Analysis Attack Complete Design Flow Differential Power Analysis |
| Content Type | Text |
| Resource Type | Article |
