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Performance evaluation of memory consistency models for shared-memory multiprocessors.
| Content Provider | CiteSeerX |
|---|---|
| Author | Gharachorloo, Kourosh |
| Abstract | The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory accesses. Several different consistency models have been proposed. These range from sequential consistency on one end, allowing very limited buffering, to release consistency on the other end, allowing extensive buffering and pipelining. The processor consistency and weak consistency models fall in between. The advantage of the less strict models is increased performance potential. The disadvantage is increased hardware complexity and a more complex programming model. To make an informed decision on the above tradeoff requires performance data for the various models. This paper addresses the issue of performance benefits from the above four consistency models. Our results are based on simulation studies done for three applications. The results show that in an environment where processor reads are blocking and writes are buffered, a significant performance increase is achieved from allowing reads to bypass previous writes. Pipelining of writes, which determines the rate at which writes are retired from the write buffer, is of secondary importance. As a result, we show that the sequential consistency model performs poorly relative to all other models, while the processor consistency model provides most of the benefits of the weak and release consistency models. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Hardware Complexity Multiprocessor Architecture Previous Writes Informed Decision Simulation Study Memory Access Processor Consistency Model Write Buffer Release Consistency Model Several Different Consistency Model Memory Consistency Model Sequential Consistency Processor Read Strict Model Limited Buffering Significant Performance Increase Various Model Performance Data Extensive Buffering Shared-memory Multiprocessor Performance Evaluation Performance Benefit Sequential Consistency Model Performs Weak Consistency Model Complex Programming Model Processor Consistency Secondary Importance Performance Potential Consistency Model |
| Content Type | Text |
| Resource Type | Article |
