Loading...
Please wait, while we are loading the content...
Similar Documents
Modelling SAMIPS: A Synthesisable Asynchronous MIPS Processor”, submitted to the 37th Annual Simulation (2004)
| Content Provider | CiteSeerX |
|---|---|
| Author | Zhang, Q. Theodoropoulos, G. |
| Description | The last fifteen years have witnessed a resurgence of interest in asynchronous digital design techniques as they promise to liberate VLSI systems from clock skew problems, offer the potential for low power and high performance and encourage a modular design philosophy which makes incremental technological migration a much easier task. This activity has revealed a need for modelling and simulation techniques suitable for the asynchronous design style. The concurrent process algebra Communication Sequential Processes (CSP) is increasingly advocated as particularly suitable for this purpose. This paper discusses the modelling of SAMIPS, a synthesisable asynchronous MIPS processor core, in Balsa, a CSP-based, asynchronous hardware description language and synthesis tool. 1 Symposium (IEEE/ACM/SCS), Part of the Advanced Simulation Technologies Conference (ASTC 2004), Hyatt Regency Crystal City |
| File Format | |
| Language | English |
| Publisher Date | 2004-01-01 |
| Access Restriction | Open |
| Subject Keyword | Synthesisable Asynchronous Mips Processor Synthesisable Asynchronous Mips Processor Core Asynchronous Design Style Incremental Technological Migration High Performance Vlsi System Modular Design Philosophy Clock Skew Problem Low Power Asynchronous Hardware Description Language Asynchronous Digital Design Technique Synthesis Tool Last Fifteen Year 37th Annual Simulation Simulation Technique |
| Content Type | Text |
| Resource Type | Article |
