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Processor modelling and code selection for retargetable compilation (2001)
| Content Provider | CiteSeerX |
|---|---|
| Author | Praet, J. Van Lanneer, D. Geurts, W. Goossens, G. |
| Abstract | Embedded processors in electronic systems typically are tuned to a few applications. Development of processor speci c compilers is prohibitively expensive and as a result such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, wedeveloped a processor model that captures the connectivity, the parallelism and all architectural peculiarities of an embedded processor. We also implemented a retargetable and optimizing compiler working on this model. We present the graph based processor model and we formally de ne the code generation task, as binding the intermediate representation of an application to this model. We also present a new method for code selection, based on this processor model, that is capable of handling directed acyclic graphs instead of trees. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors Code generation� |
| File Format | |
| Volume Number | 6 |
| Journal | ACM Tr. Design Autom. of Electronic Systems |
| Language | English |
| Publisher Date | 2001-01-01 |
| Access Restriction | Open |
| Subject Keyword | Code Selection Processor Model Retargetable Compilation Processor Modelling Subject Descriptor Processor Code Generation Yield Code Intermediate Representation Code Generation Task Unacceptable Quality Programming Language Electronic System Acyclic Graph Processor Speci Compiler Result Compiler Embedded Processor New Method Architectural Peculiarity Code Quality |
| Content Type | Text |
| Resource Type | Article |
