Using Switch Directories to Speed Up Cache-to-Cache Transfers (2000)

Content Provider	CiteSeerX
Author	Iyer, Ravi Bhuyan, Laxmi N. Nanda, Ashwini
Description	In CCNUMA Multiprocessors”. Proc. of the 14th Int’l Parallel and Distributed Processing Symposium (IPDPS’00 In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implement small fast directory caches in crossbar switches of the interconnect medium to capture and store ownership information as the data flows from the memory module to the requesting processor. Using the stored information, the switch directory re-routes subsequent requests to dirty blocks directly to the owner cache, thus reducing the latency for home node processing such as slow DRAM directory access and coherence controller occupancies. The design and implementation details of a DiRectory Embedded Switch ARchitecture, DRESAR, are presented. We explore the performance benefits of switch directories by modeling DRESAR in a detailed execution driven simulator. Our results show that the switch directories can improve performance by up to 60 % reduction in home node cache-to-cache transfers for several scientific applications and commercial workloads. 1
File Format	PDF
Language	English
Publisher Date	2000-01-01
Access Restriction	Open
Subject Keyword	Slow Dram Directory Access Small Fast Directory Cache Directory Embedded Switch Architecture Commercial Workload Requesting Processor Communication Latency Home Node Processing Main Idea Home Node Cache-to-cache Transfer Interconnect Medium Novel Hardware Switch Directory Re-routes Subsequent Request Coherence Controller Occupancy Owner Cache Crossbar Switch Cache-to-cache Transfer Detailed Execution Several Scientific Application Store Ownership Information Stored Information Implementation Detail Performance Benefit Switch Directory Cc-numa Multiprocessor Memory Module
Content Type	Text
Resource Type	Article