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A 4-bit multiplier using a two phase drive adiabatic dynamic cmos logic.
| Content Provider | CiteSeerX |
|---|---|
| Author | Sekine, Toshikazu Takahashi, Yasuhiro Yokoyama, Michio |
| Abstract | Abstract: This paper describe the design and VLSI implementation of a multiplier using an adiabatic logic which is called a two phase drive adiabatic dynamic CMOS logic (2PADCL) circuit. Circuit operation and performance has been evaluated using a 4×4-bit 2PADCL multiplier fabricated in a 1.2 µm CMOS process. The experimental results show that the multiplier was operated with clock frequencies 800kHz. The total power dissipation of the 4×4-bit 2PADCL multiplier was also 5.19 mW at the 1.5 VDC power supply voltage. 1. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Clock Frequency Cmos Process Vdc Power Supply Voltage 4-bit Multiplier Circuit Operation Vlsi Implementation Total Power Dissipation Adiabatic Logic Experimental Result |
| Content Type | Text |
| Resource Type | Article |
