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A 50 Mbit/s Iterative Turbo-Decoder (2000)
| Content Provider | CiteSeerX |
|---|---|
| Author | Piccinini, Viglione Masera Viglione, F. Masera, G. Piccinini, G. Roch, M. Ruo Zamboni, M. |
| Description | Very low bit error rate has become an important constraint in high performance communication systems that operate at very low signal to noise ratios: due to their impressive coding gains, turbo codes have been proposed for several applications, although they suffer a large decoding delay. This paper presents the design of a turbo decoder with high performances in terms of throughput implemented using TSPC (True Single Phase Clocking) logic family. In order to achieve the best compromise between cost (in terms of area) and throughput, several architectural solutions have been analyzed. The whole system and in particular its core, the SISO module, has been verified through VHDL simulations. HSPICE simulations show that the system can operate with a 1 GHz clock and thus it can reach a throughput of 50 Mbit/s. Proc. Design, Automation and Test in Europe Conf. (DATE |
| File Format | |
| Language | English |
| Publisher Date | 2000-01-01 |
| Access Restriction | Open |
| Subject Keyword | Several Application Whole System Siso Module High Performance Communication System Important Constraint Ghz Clock True Single Phase Clocking Several Architectural Solution High Performance Hspice Simulation Low Signal Low Bit Error Rate Vhdl Simulation Mbit Iterative Turbo-decoder Turbo Code Large Decoding Delay Impressive Coding Gain Turbo Decoder |
| Content Type | Text |
| Resource Type | Article |
