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An efficient circulant mimo equalizer for cdma downlink: algorithm and vlsi architecture (2005).
| Content Provider | CiteSeerX |
|---|---|
| Author | Zhang, Jianzhong Charlie Guo, Yuanbin Cavallaro, Joseph R. Mccain, Dennis |
| Abstract | In this paper, we present an efficient circulant approximation based MIMO equalizer architecture for the CDMA downlink. This reduces the Direct-Matrix-Inverse (DMI) of size (NF × NF) with O((NF) 3) complexity to some FFT operations with O(NF log 2(F)) complexity and the inverse of some (N × N) sub-matrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the (4 × 4) high-order receiver from partitioned (2 × 2) sub-matrices. This leads to more parallel VLSI design with 3 × further complexity reduction. Comparative study with both the Conjugate-Gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C High-Level-Synthesis methodology. |
| File Format | |
| Publisher Date | 2005-01-01 |
| Access Restriction | Open |
| Subject Keyword | Catapult High-level-synthesis Methodology Dmi Algorithm Cdma Downlink Comparative Study Efficient Circulant Mimo Equalizer Reduced-state Fft Fft Operation Area Time Efficiency Parallel Vlsi Design Hermitian Optimization Nf Nf Complexity Optimization Efficient Circulant Approximation Promising Performance Complexity Tradeoff Complexity Reduction Generic Vlsi Architecture High-order Receiver Mimo Equalizer Architecture Vlsi Architecture Vlsi Design Space Layered Parallelism |
| Content Type | Text |
