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Digital circuit signal integrity enhancement by monitoring power grid activity 1.
| Content Provider | CiteSeerX |
|---|---|
| Author | Teixeira, J. P. Andina, J. J. Rodríguez Teixeira, I. C. Piccoli, L. Santos, M. B. Semião, J. Rodriguez-Irago, M. Vargas, F. |
| Abstract | As IC technology scales down, interconnect issues are becoming one of the major concerns of gigahertz System-on-Chip (SoC) design. Voltage distortion (power supply noise) and delay violations (signal and clock skews) dramatically contribute to signal integrity loss. As a consequence, performance degradation, reliability problems and ultimately, functional error occur. In this paper, we propose a new methodology to enhance SoC signal integrity with respect to power/ground voltage transients, without degrading its performance. The underlying principle of the proposed methodology is to dynamically adapt the clock duty-cycle (CDC) according to the signal propagation delay through the logic whose power supply voltage is being disturbed. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Functional Error Occur Interconnect Issue Clock Duty-cycle Reliability Problem Ic Technology Scale Signal Integrity Loss Power Ground Voltage Transient Digital Circuit Signal Integrity Enhancement Power Supply Voltage Power Supply Noise New Methodology Delay Violation Performance Degradation Clock Skews Signal Propagation Delay Major Concern Soc Signal Integrity Gigahertz System-on-chip Power Grid Activity Underlying Principle |
| Content Type | Text |
