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Comparative analysis of serial vs parallel.
| Content Provider | CiteSeerX |
|---|---|
| Author | Cidon, Arkadiy Morgenshtein Israel |
| Abstract | Analytical model is employed to characterize and compare serial and parallel communication techniques in NoC interconnect. Simulations that are based on 130nm and 70nm technology parameters reveal up to ×5.5 and ×17 reduction in power and area of serial vs. 32-bit multi-layer parallel link, respectively. Lower power is dissipated by a single-layer parallel link but it occupies larger area. We conclude that long on-chip interconnects could benefit from serial links. II. SERIALIZER STRUCTURE The transformation of parallel multi-bit signal flow into a serial line and vice-versa requires special units at both ends of the link. The Serializer and De-serializer interface the router/module to the serial link. The serializer converts m-bit parallel data into serial form. It must operate at high speed to compensate for the loss of parallelism. This creates a challenging trade-off between transistor scaling and compact, low-power implementation. I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Low-power Implementation Parallel Communication Technique Serial Line M-bit Parallel Data Parallel Multi-bit Signal Flow Single-layer Parallel Link Noc Interconnect Serial Link Router Module Special Unit Analytical Model Serial Form Comparative Analysis Serial V Parallel High Speed Technology Parameter On-chip Interconnects Serializer Structure 32-bit Multi-layer Parallel Link Serial V Transistor Scaling |
| Content Type | Text |
