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7a-2 skew scheduling and clock routing for improved tolerance to process variations*.
| Content Provider | CiteSeerX |
|---|---|
| Author | Hu, Jiang Sze, C. N. Venkataraman, Ganesh |
| Abstract | Abstract The synthesis of clock network in she presence of process variation is becoming a vital design issue towards the performunce of digiti11 circuits. In this paper, we propose a clock tree design ulgorithm which is driven by the tolerance towards process variutions. We consider tolerance to process variation in various stages of clock tree synthesis which in-clude clock skew scheduling, abstract tree generation'and luy-OMI embedding. The primary objective of this work is to min-imize the maximum skew violation and a layout embedding technique spec$cally targeting this objective is detuiled. Ex-perimental results indicate the our proposed procedure leads to significant reduction in maximum skew violation due to pro-cess variation with negligible change in wire length. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Wire Length Negligible Change Significant Reduction In-clude Clock Skew Scheduling Process Variation 7a-2 Skew Scheduling Clock Tree Design Ulgorithm Abstract Tree Generation Maximum Skew Violation Vital Design Issue Clock Tree Synthesis Technique Spec Pro-cess Variation Clock Routing Ex-perimental Result Digiti11 Circuit Luy-omi Embedding Primary Objective Various Stage Clock Network Tolerance Towards Process Variutions Improved Tolerance |
| Content Type | Text |
