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Instruction Fetching: Coping with Code Bloat (1995)
| Content Provider | CiteSeerX |
|---|---|
| Author | Uhlig, Richard |
| Description | Previous research has shown that the SPEC benchmarks achieve low miss ratios in relatively small instruction caches. This paper presents evidence that current software-development practices produce applications that exhibit substantially higher instruction-cache miss ratios than do the SPEC benchmarks. To represent these trends, we have assembled a collection of applications, called the Instruction Benchmark Suite (IBS), that provides a better test of instruction-cache performance. We discuss the rationale behind the design of IBS and characterize its behavior relative to the SPEC benchmark suite. Our analysis is based on trace-driven and trap-driven simulations and takes into full account both the application and operating-system components of the workloads. This paper then reexamines a collection of previously-proposed hardware mechanisms for improving instruction-fetch performance In Proceedings of the 22nd Annual International Symposium on Computer Architecture |
| File Format | |
| Language | English |
| Publisher Date | 1995-01-01 |
| Access Restriction | Open |
| Subject Keyword | Instruction-cache Miss Ratio Instruction-fetch Performance Instruction Benchmark Suite Low Miss Ratio Spec Benchmark Instruction-cache Performance Current Software-development Practice Small Instruction Cache Full Account Code Bloat Trap-driven Simulation Behavior Relative Previously-proposed Hardware Mechanism Spec Benchmark Suite Operating-system Component Previous Research |
| Content Type | Text |
| Resource Type | Article |
