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Hardware Implementation of Stack-Based Replacement Algorithms
| Content Provider | CiteSeerX |
|---|---|
| Author | Ghasemzadeh, Hassan Moghaddam, Hassan Goldani Mazrouee, Sepideh |
| Abstract | Abstract—Block replacement algorithms to increase hit ratio have been extensively used in cache memory management. Among basic replacement schemes, LRU and FIFO have been shown to be effective replacement algorithms in terms of hit rates. In this paper, we introduce a flexible stack-based circuit which can be employed in hardware implementation of both LRU and FIFO policies. We propose a simple and efficient architecture such that stack-based replacement algorithms can be implemented without the drawbacks of the traditional architectures. The stack is modular and hence, a set of stack rows can be cascaded depending on the number of blocks in each cache set. Our circuit can be implemented in conjunction with the cache controller and static/dynamic memories to form a cache system. Experimental results exhibit that our proposed circuit provides an average value of 26 % improvement in storage bits and its maximum operating frequency is increased by a factor of two |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Hardware Implementation Basic Replacement Scheme Hit Ratio Abstract Block Replacement Algorithm Fifo Policy Stack-based Replacement Algorithm Cache Memory Management Efficient Architecture Effective Replacement Algorithm Static Dynamic Memory Hit Rate Cache System Storage Bit Cache Controller Average Value Experimental Result Stack Row Maximum Operating Frequency Flexible Stack-based Circuit Traditional Architecture |
| Content Type | Text |
