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Thread-Sensitive Instruction Issue for SMT Processors
| Content Provider | CiteSeerX |
|---|---|
| Author | Robatmili, Behnam Sardashti, Somayeh Nourani, Mehrdad Yazdani, Nasser |
| Abstract | Abstract—Simultaneous Multi Threading (SMT) is a processor design method in which concurrent hardware threads share processor resources like functional units and memory. The scheduling complexity and performance of an SMT processor depend on the topology used in the fetch and issue stages. In this paper, we propose a thread sensitive issue policy for a partitioned SMT processor which is based on a thread metric. We propose the number of ready-to-issue instructions of each thread as priority metric. To evaluate our method, we have developed a reconfigurable SMT-simulator on top of the SimpleScalar Toolset. We simulated our modeled processor under several workloads composed of SPEC benchmarks. Experimental results show around 30 % improvement compared to the conventional OLDEST_FIRST mixed topology issue policy. Additionally, the hardware implementation of our architecture with this metric in issue stage is quite simple I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Ready-to-issue Instruction Issue Stage Hardware Implementation Scheduling Complexity Modeled Processor Thread Sensitive Issue Policy Spec Benchmark Smt Processor Depend Smt Processor Several Workload Thread-sensitive Instruction Issue Experimental Result Simplescalar Toolset Processor Design Method Reconfigurable Smt-simulator Functional Unit Abstract Simultaneous Multi Threading Partitioned Smt Processor |
| Content Type | Text |
