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Frame detection in high bit-rate cmos systems.
| Content Provider | CiteSeerX | 
|---|---|
| Abstract | ABSTRACT- This paper presents a technique for frame synchronization in high-speed telecommunications systems. The described structure allows frame synchronization to be performed independently from the technology inherent delays, resorting to a parallel data pattern detector and a bit alignment shifter. The principle has been implemented in a 0.8 μm CMOS SDH/STM-4 (622 Mb/s) system. I. | 
| File Format | |
| Access Restriction | Open | 
| Subject Keyword | Frame Synchronization Bit Alignment Shifter High-speed Telecommunication System Technology Inherent Delay Described Structure Parallel Data Pattern Detector Cmos Sdh Stm-4 | 
| Content Type | Text | 
| Resource Type | Article | 
 
					