NDLI: Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories 1.

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Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories 1.

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Abstract	This paper introduces the architecture and initial algorithms for Pixel-Planes 5, a heterogeneous multi-computer designed both for high-speed polygon and sphere rendering (1M Phong-shaded tri-angles/second) and for supporting algorithm and application re-search in interactive 3D graphics. Techniques are described for volume rendering at multiple frames per second, font generation directly from conic spline descriptions, and rapid calculation of radiosity form-factors. The hardware consists of up to 32 math-oriented processors, up to 16 rendering units, and a conventional 1280x1024-pixel frame buffer, interconnected by a 5 gigabit ring network. Each rendering unit consists of a 128x 128-pixel array of processors-with-memory with parallel quadratic expression evalu-ation for every pixel. Implemented on 1.6 micron CMOS chips designed to run at 40MHz, this array has 208 bits/pixel on-chip and is connected to a video RAM memory system that provides 4,096 bits of off-chip memory. Rendering units can be independently reas-signed to any part of the screen or to non-screen-oriented computa-tion. As of April 1989, both hardware and software are still under construction, with initial system operation scheduled for fall 1989.
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Access Restriction	Open
Subject Keyword	Math-oriented Processor Initial System Operation Parallel Quadratic Expression Evalu-ation Multiple Frame High-speed Polygon Initial Algorithm Conic Spline Description Sphere Rendering Application Re-search Video Ram Memory System Gigabit Ring Network Off-chip Memory Micron Cmos Chip Conventional 1280x1024-pixel Frame Buffer Non-screen-oriented Computa-tion 128-pixel Array Radiosity Form-factors Heterogeneous Multi-computer Phong-shaded Tri-angles Rapid Calculation Font Generation
Content Type	Text
Resource Type	Article

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