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New methods for parallel pattern. (1993).
| Content Provider | CiteSeerX |
|---|---|
| Author | Mojtahedi, Mehrdad Geisselhardt, Walter |
| Abstract | This paper describes COMBINED, a super fast fault simulator for synchronous sequential circuits. COMBINED results from coupling a parallel pattern simulator with a nonparallel simulator both working based on single fault propagation. Circuit partitioning and removing all feedback loops implemented into the parallel part of COMBINED result in a reduction of the number of events. In addition, the nonparallel part of COMBINED has been expanded either to detect more faults by introducing restricted symbolic fault simulation, or to reduce the number of events using PStarAlgorithm which are also presented in this paper. COMBINED runs substantially faster on ISCAS-89 benchmark circuits than a state-of-the-art single fault |
| File Format | |
| Publisher Date | 1993-01-01 |
| Access Restriction | Open |
| Subject Keyword | Super Fast Fault Simulator Parallel Pattern Simulator Parallel Pattern Nonparallel Part State-of-the-art Single Fault Nonparallel Simulator Iscas-89 Benchmark Circuit Single Fault Propagation Combined Result Circuit Partitioning Parallel Part Synchronous Sequential Circuit Symbolic Fault Simulation New Method |
| Content Type | Text |
| Resource Type | Article |
