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Composable lightweight processors (2007)
| Content Provider | CiteSeerX |
|---|---|
| Author | Kim, Changkyu Sethumadhavan, Simha Govindan, M. S. Ranganathan, Nitya Gulati, Divya Burger, Doug Keckler, Stephen W. |
| Description | Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processors. However, the number of processors and the granularity of each processor are fixed at design time. This paper evaluates a flexible architectural approach, called Composable Lightweight Processors (or CLPs), that allows simple, low-power cores to be aggregated together dynamically, forming larger, more powerful single-threaded processors without changing the application binary. We evaluate one such design with 32 cores called TFlex, which can be configured as 32 dual-issue processors, or as a single 64-wide issue processor, or as any point in between. Use of an Explicit Data Graph Execution (EDGE) ISA enables the system to be fully composable, with no monolithic structures spanning the cores. Simulation results show that CLPs achieve an average performance boost of 42%, an average area-efficiency of 3.4x, and an average power-efficiency of 2x over a fixed architecture on a spectrum of single-threaded applications. Results also show that CLPs outperform a spectrum of fixed CMP architectures on a set of multitasking workloads. 1 |
| File Format | |
| Language | English |
| Publisher | IEEE Computer Society |
| Publisher Date | 2007-01-01 |
| Publisher Institution | In Proceedings of the 40th International Symposium of Microarchitecture |
| Access Restriction | Open |
| Subject Keyword | Modern Chip Multiprocessor Single 64-wide Issue Processor Fixed Architecture Flexible Architectural Approach Composable Lightweight Processor Average Area-efficiency Average Performance Boost Dual-issue Processor Single-threaded Application Monolithic Structure Application Binary Thread-level Parallelism Powerful Single-threaded Processor Simulation Result Low-power Core Instruction-level Parallelism Design Time Average Power-efficiency Explicit Data Graph Execution Fixed Cmp |
| Content Type | Text |
| Resource Type | Article |
