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| Content Provider | The American Society of Mechanical Engineers (ASME) Digital Collection |
|---|---|
| Author | Islam, Nokibul Jimarez, Miguel Syed, Ahmer Hwang, Taekyeong Gim, Jaeyun Kang, Wonjoon |
| Copyright Year | 2011 |
| Abstract | Flip Chip (FC) technology has now become the mainstream solution for high performance packages. From commercial gaming machines to high reliability servers, the FC package is gaining more market share over traditional packaging technologies, such as wire bond. Extensive research has been carried out to make the flip chip more robust, smaller foot prints, and excellent performance. FC packages are fabricated typically in two main configurations. Bare die FC packages leave the non active side of the die exposed. This allows the customer to apply their preferred heat dissipation scheme during board level attach. Lidded FC packages use a metallic lid attached to the die. Bare die package can be further subdivided into bare die underfilled package and bare die flip chip molded ball grid array (FCmBGA) package. Each of these packaging configurations has advantages as well as disadvantages. FCmBGA uses molding compound or EMC instead of capillary underfill, to protect FC die, and eliminate the need for a lid. Package warpage reduced a lot by adding a lid with the bare die FC package. However, the package and board level reliability for the above package types are still debatable. In this study test vehicles with three package types with bumps and BGAs are daisy chain to measure in situ data during accelerated tests. Impact of standard vs. low CTE (coefficient of thermal expansion) core substrate, accelerated temperature cycle conditions (temperature cycle condition “B”, “H”, and “J” according to JEDEC), and package level vs. package mounted on the board level reliability will be investigated. Comprehensive reliability data will help to select the right package type for next generation large die large body flip chip application. |
| Sponsorship | Electronic and Photonic Packaging Division |
| Starting Page | 609 |
| Ending Page | 615 |
| Page Count | 7 |
| File Format | |
| ISBN | 9780791844618 |
| DOI | 10.1115/IPACK2011-52260 |
| Volume Number | ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1 |
| Conference Proceedings | ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems |
| Language | English |
| Publisher Date | 2011-07-06 |
| Publisher Place | Portland, Oregon, USA |
| Access Restriction | Subscribed |
| Subject Keyword | Underfill Eol Tc-b Warpage Lead free Tc-j Flip chip Tc-h Spl Mrt Fcmbga Reliability Delamination Flip-chip devices Ball-grid-array packaging Warping Flip-chip |
| Content Type | Text |
| Resource Type | Article |
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