NDLI: Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems (OM '01)

Content Provider	ACM Digital Library
Author	Kang, Dong-In Crago, Stephen Suh, Jinwoo
Abstract	This paper presents an end-to-end synthesis technique for low-power distributed real-time system design. This technique synthesizes supply voltages of resources to optimize system-level power consumption while satisfying end-to-end hard real-time latency bounds. A system is modeled as a set of distributed task chains (or pipelines). Each task chain is given its own end-to-end constraints. Task chains may share resources. Our approach searches the space of the trade-off between end-to-end latency and supply voltages of resources to minimize system-level power consumption. A power optimization algorithm is proposed for simple distributed real-time systems that do not have any resource sharing between task chains, and its optimality is shown. For more general systems, a heuristic based on the same techniques is proposed.
Starting Page	20
Ending Page	28
Page Count	9
File Format	PDF
ISBN	1581134266
DOI	10.1145/384198.384203
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2001-08-01
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Voltage scaling Synthesis Real-time Distributed system
Content Type	Text
Resource Type	Article

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Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems (OM '01)