NDLI: Vectorizing Unstructured Mesh Computations for Many-core Architectures

Please wait, while we are loading the content...

Autotuning Wavefront Applications for Multicore Multi-GPU Hybrid Architectures

Reduction Operations in Parallel Loops for GPGPUs

Self-Configuration and Self-Optimization Autonomic Skeletons using Events

Programming a Multicore Architecture without Coherency and Atomic Operations

Vectorizing Unstructured Mesh Computations for Many-core Architectures

Compiling Fresh Breeze Codelets

A Framework for Multiplatform HPC Applications

A Novel CPU-GPU Cooperative Implementation of A Parallel Two-List Algorithm for the Subset-Sum Problem

Dynamic Partitioning-based JPEG Decompression on Heterogeneous Multicore Architectures

Fast Longest Common Subsequence with General Integer Scoring Support on GPUs

Efficient Parallel Implementations of Multiple Sequence Alignment using BSP/CGM Model

Work Stealing Strategies For Multi-Core Parallel Branch-and-Bound Algorithm Using Factorial Number System

Palirria: Accurate On-line Parallelism Estimation for Adaptive Work-Stealing

DWS: Demand-aware Work-Stealing in Multi-programmed Multi-core Architectures

Reachability Analysis of Cost-Reward Timed Automata for Energy Efficiency Scheduling

Vectorizing Unstructured Mesh Computations for Many-core Architectures

Content Provider	ACM Digital Library
Author	László, E. Mudalige, G. R. Reguly, I. Z. Giles, M. B.
Abstract	Achieving optimal performance on the latest multi-core and many-core architectures depends more and more on making efficient use of the hardware's vector processing capabilities. While auto-vectorizing compilers do not require the use of vector processing constructs, they are only effective on a few classes of applications with regular memory access and computational patterns. Irregular application classes require the explicit use of parallel programming models; CUDA and OpenCL are well established for programming GPUs, but it is not obvious what model to use to exploit vector units on architectures such as CPUs or the Xeon Phi. Therefore it is of growing interest what programming models are available, such as Single Instruction Multiple Threads (SIMT) or Single Instruction Multiple Data (SIMD), and how they map to vector units. This paper presents results on achieving high performance through vectorization on CPUs and the Xeon Phi on a key class of applications: unstructured mesh computations. By exploring the SIMT and SIMD execution and parallel programming models, we show how abstract unstructured grid computations map to OpenCL or vector intrinsics through the use of code generation techniques, and how these in turn utilize the hardware. We benchmark a number of systems, including Intel Xeon CPUs and the Intel Xeon Phi, using an industrially representative CFD application and compare the results against previous work on CPUs and NVIDIA GPUs to provide a contrasting comparison of what could be achieved on current many-core systems. By carrying out a performance analysis study, we identify key performance bottlenecks due to computational, control and bandwidth limitations. We show that the OpenCL SIMT model does not map efficiently to CPU vector units due to auto-vectorization issues and threading overheads. We demonstrate that while the use of SIMD vector intrinsics imposes some restrictions, and requires more involved programming techniques, it does result in efficient code and near-optimal performance, that is up to 2 times faster than the non-vectorized code. We observe that the Xeon Phi does not provide good performance for this class of applications, but is still on par with a pair of high-end Xeon chips. CPUs and GPUs do saturate the available resources, giving performance very near to the optimum.
Starting Page	39
Ending Page	50
Page Count	12
File Format	PDF
ISBN	9781450326575
DOI	10.1145/2560683.2560686
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-02-07
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Domain specific library Op2 Avx Xeon phi Unstructured grid Vectorization Cuda
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in