NDLI: Deadline-monotonic software scheduling for the co-synthesis of parallel hard real-time systems

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A prototype VLSI chip architecture for JPEG image compression

A variant of Cooley-Tuckey algorithm with local memory management

Eliminating the Z-Buffer bottleneck

Defect-oriented test methodology for complex mixed-signal circuits

A design-for-test structure for optimising analogue and mixed signal IC test

Mixed-signal circuits and boards for high safety applications

Exact scheduling strategies based on bipartite graph matching

On applicability of symbolic techniques to larger scheduling problems

Optimizing synchronous systems for multi-dimensional applications

When clusters meet partitions: new density-based methods for circuit decomposition

Circuit clustering for delay minimization under area and pin constraints

Architecture driven k-way partitioning for multichip modules

Synthesis of multilevel fault-tolerant combinational circuits

Improved technology mapping using a new approach to Boolean matching

Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions

Low-voltage low-power switched-current circuits and systems

Low supply voltage, low noise fully differential programmable gain amplifiers

A universal telephone audio circuit with loudhearing and handsfree operation in CMOS technology

A flexible topology selection program as part of an analog synthesis system

Pseudo-exhaustive word-oriented DRAM testing

Functional test for shifting-type FIFOs

A 370-MHz memory built-in self-test state machine

Modeling and optimization of hierarchical synchronous circuits

Improving initialization through reversed retiming

Elimination of multi-cycle false paths by state encoding

Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMC

Post-layout optimization of power and timing for ECL LSIs

A 622/155 mbps ATM line terminator mono-chip

A unified model for co-simulation and co-synthesis of mixed hardware/software systems

SLIF: a specification-level intermediate format for system design

Deadline-monotonic software scheduling for the co-synthesis of parallel hard real-time systems

High-level synthesis for easy testability

Sequential logic minimization based on functional testability

A Gauss-elimination based PRPG for combinational circuits

Mixed-signal modelling in VHDL for system-on-chip applications

Run-time consistency checking in discrete simulation models

Delay models for the sea-of-wires array synthesis system

A unified scheduling model for high-level synthesis and code generation

A BDD-based frontend for retargetable compilers

Efficient code generation for in-house DSP-cores

Complexity of sequential ATPG

Improved sequential ATPG using functional observation information and new justification methods

GARDA: a diagnostic ATPG for large synchronous sequential circuits

Controlling change propagation and project policies in IC design

Generic design flows for project management in a framework environment

Enhanced functionality by coupling the JESSI-COMMON-Framework with an ECAD framework

Enhanced testing performance via unbiased test sets

A testability measure for hierarchical design environments

Gate delay fault test generation for non-scan circuits

Verifying real-time properties of MOS-transistor circuits

Using symbolic techniques to find the maximum clique in very large sparse graphs

Checking signal transition graph implementability by symbolic BDD traversal

Proving testing preorders for process algebra descriptions

Architectural exploration for datapaths with memory hierarchy

Design reuse through high-level library mapping

Automatic clock tree generation in ASIC designs

Area versus detection latency trade-offs in self-checking memory design

Self-checking architectures for fast Hartley transform

Built-in intermediate voltage testing for CMOS circuits

Design and test of the PowerPC 603 microprocessor

An ASIC design for real-time image processing in industrial applications

Rapid prototype of a hardware emulator for a SIMD processor array

Analysis and reduction of glitches in synchronous networks

Decomposition of logic functions for minimum transition activity

Prediction of interconnect delay in logic synthesis

A BIST approach to delay fault testing with reduced test length

BIST hardware generator for mixed test scheme

Accumulator-based BIST approach for stuck-open and delay fault testing

How many decomposition types do we need? [decision diagrams]

VERIFUL: VERIfication using FUnctional Learning

Implicit manipulation of polynomials using zero-suppressed BDDs

Automatic test vector generation for mixed-signal circuits

Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits

Achieving simulation-based test program verification and fault simulation capabilities for mixed-signal systems

The effect of pin constraints on layout area

EMC-driven midway routing on PCBs

A hybrid hierarchical approach for multi-layer global routing

Software estimation using a generic-processor model

Describing instruction set processors using nML

Incorporating compiler feedback into the design of ASIPs

An efficient method for computing exact path delay fault coverage

Bit parallel test pattern generation for path delay faults

A trace-based method for delay fault diagnosis in synchronous sequential circuits

Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures

On software development to support statistical simulation of analogue circuits

Multilevel thermal simulation of MCM's by system 'MONSTR-M'

Combining MBP-speculative computation and loop pipelining in high-level synthesis

PPS: a pipeline path-based scheduler

Balancing structural hazards and hardware cost of pipelined processors

Correlation between I/sub DDQ/ testing quality and sensor accuracy

Synthesis of I/sub DDQ/-testable circuits: integrating built-in current sensors

A built-in quiescent current monitor for CMOS VLSI circuits

High speed communications links for ASICs

TRJM: a high speed programmable ATM-SDH mapper

Artificial neural networks in medical decision making systems: an application to pulmonary diseases' diagnosis through VHDL synthesis

Integration of an expert system for analogue layout synthesis into a commercial CAD framework

Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams

Efficient synthesis of fault-tolerant controllers

A balanced multilevel decomposition method

A precise event-driven circuit simulator based on predicted fan-in voltages

Network initialization in a switch-level simulator

SENSAT-a practical tool for estimation of the IC layout sensitivity to spot defects

A novel DFT technique for critical bridging faults in CMOS and BiCMOS ICs

A method for testability analysis and BIST insertion at the RTL

Thermal test and monitoring [microelectronic structures]

On testability of checkable digital circuits under pseudorandom signals

Imperfect linear duplication of combinational circuits

Test preparation methodology for high coverage of physical defects in CMOS digital ICs

Fully automatic DC fault dictionary construction and test nodes selection for analogue fault diagnosis

A comparative study of algorithms for A/D converter performance evaluation by statistical analysis

A histogram method for analog-digital converters testing in time and spectral domain

Index of Authors

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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