NDLI: The Bel array: asynchronous fine-grained reconfigurable co-processing

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The Bel array: asynchronous fine-grained reconfigurable co-processing

Content Provider	ACM Digital Library
Author	Beckett, Paul Przybylski, Andrew Haque, Kashfia
Abstract	This paper presents the Bit-Element (Bel) Array, a single-bit asynchronous reconfigurable 2D array designed using NULL Convention Logic (NCL), set up for co-processing applications. Each Bel can develop any Boolean function of its two inputs, thereby supporting logic, routing or constant generation. The fine-grained reconfigurable fabric exhibits spatial computing characteristics that can provide massive parallelism within and across computational graphs. Asynchronous NCL implementation enables operation over a broad voltage range to suit (slower) low power operation, or low latency and high performance, at higher power. An example simulation of a 20-Tap SWL FIR exhibits a wide operating range from 200MSPS at 0.6V (2.8mW), up to 2.8GSPS at 1.2V (42.53mW). Comparing throughput performance, the Bel Array operates at just over one quarter of the power density of an equivalent high performance commercial FPGA.
Starting Page	1
Ending Page	4
Page Count	4
File Format	PDF
ISBN	9781450347686
DOI	10.1145/3014812.3014859
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2017-01-30
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Fine-grained Null convention logic Spatial computing Asynchronous circuits Reconfigurable
Content Type	Text
Resource Type	Article

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